Figure 2–8 – Altera Nios Development Board Cyclone II Edition User Manual
Page 34
2–22
Reference Manual
Altera Corporation
Nios Development Board Cyclone II Edition
May 2007
Board Components
Figure 2–8. PROTO2 Expansion Prototype Connector - J15, J16 & J17
V17
39
J16
proto2_io28
J15
AE17
3
J15
proto2_io40
AB18
4
J15
proto2_io29
AC18
5
J15
proto2_io30
AF19
6
J15
proto2_io31
AE19
7
J15
proto2_io32
AF18
8
J15
proto2_io33
AE18
9
J15
proto2_io34
AA16
10
J15
proto2_io35
Y16
11
J15
proto2_io36
AC17
12
J15
proto2_io37
AD17
13
J15
proto2_io38
AF17
14
J15
proto2_io39
J17
U2 pin 18
9
J17
proto2_osc
F20
11
J17
proto2_pllclk
AF14
13
J17
proto2_clkout
Table 2–12. PROTO2 Pin Table (Continued)
FPGA Pin
PROTO2 Pin
Connector
Board Net Name
Pin 1
J15
J17
J16
Pin 1
Pin 1
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)