Altera Nios Development Board Cyclone II Edition - Manual (Page 24)

2–12 Reference Manual Altera Corporation
Nios Development Board Cyclone II Edition May 2007
Board Components
The on-board configuration controller makes assumptions about what-
resides-where in flash memory. For details refer to
“SW10 – Reset,
Config” on page 2–35 .
f
See www.amd.com for detailed information about the flash memory
device.
E15 4 fe_a15
H15 3 fe_a16
H16 54 fe_a17
A17 19 fe_a18
B17 18 fe_a19
G15 11 fe_a20
F15 12 fe_a21
F16 15 fe_a22
G16 2 fe_a23
D8 35 fe_d0
C8 37 fe_d1
F10 39 fe_d2
G10 41 fe_d3
D9 44 fe_d4
C9 46 fe_d5
B8 48 fe_d6
A8 50 fe_d7
H17 32 flash_cs_n
F17 34 flash_oe_n
G17 13 flash_rw_n
B18 16 flash_wp_n
C17 53 flash_byte_n (1)
D17 17 flash_ry_by_n
Note to Table 2–8 :
(1) BYTE_n on U5 is pulled low to keep the flash memory in byte
mode which restricts the usable modes of operation.
Table 2–8. Flash Memory Pin Table (Continued)
FPGA Pin U5 Pin Board Net Name