Altera Nios Development Board Cyclone II Edition - Manual (Page 19)

Altera Corporation Reference Manual 2–7
May 2007 Nios Development Board Cyclone II Edition
Board Components
Table 2–6 shows all connections between the FPGA and the SSRAM chip.
Table 2–6. SSRAM Pin Table
FPGA Pin U74 Pin Pin Function Board Net Name
AB3 37 A0 ssram_a0
AB4 36 A1 ssram_a1
G5 35 A2 ssram_a2
G6 34 A3 ssram_a3
B2 33 A4 ssram_a4
B3 32 A5 ssram_a5
C2 38 NC/A19 ssram_a6
C3 39 NC/A20 ssram_a7
L9 42 A6 ssram_a8
F7 43 A7 ssram_a9
L10 44 A8 ssram_a10
J5 45 A9 ssram_a11
L4 46 A10 ssram_a12
C6 47 A11 ssram_a13
A4 48 A12 ssram_a14
B4 49 A13 ssram_a15
A5 50 A14 ssram_a16
B5 81 A15 ssram_a17
B6 82 A16 ssram_a18
A6 99 A17 ssram_a19
C4 100 A18 ssram_a20
G9 85 ADSC_N ssram_adsc_n
M3 93 BE_n0 ssram_be_n0
M2 94 BE_n1 ssram_be_n1
M4 95 BE_n2 ssram_be_n2
M5 96 BE_n3 ssram_be_n3
C7 98 CE1_n ssram_ce1_n
L2 52 D0 ssram_d0
L3 53 D1 ssram_d1
L7 56 D2 ssram_d2
L6 57 D3 ssram_d3
N9 58 D4 ssram_d4