Board components, Component list, Chapter 2. board components – Altera Nios Development Board Cyclone II Edition User Manual
Page 13: Component list –1, User interface
Altera Corporation
2–1
May 2007
2. Board Components
Component List
This section introduces all the important components on the Nios
development board. See
for component
locations and brief descriptions of all board features.
Figure 2–1. Nios Development Board
J26
D34
J19
RJ1
J24
LED7
LED6
TP1–
TP8
U5
U4
U3
U74
U63
U62
U8
U9
J4
JH1
JH2
Y2
J25
J5
J27
U69
SW0 – SW3
Reset, Config
(SW10)
CON3
D0 – D7
CPU Reset
(SW8)
Factory Config
(SW9)
Optional Power
Optional Power
Supply
Supply
Optional Power
Supply
PROTO1
(J11, J12, J13)
PROTO2
(J15, J16, J17)
Table 2–1. Nios Development Board, Cyclone II Edition Components & Interfaces
Board Designation
Name
Description
U62
Cyclone II FPGA
EP2C35F672C5 or EP2C35F672C5N device.
User Interface
SW0 – SW3
Push-button switches
Four momentary contact switches for user input to the
FPGA.
D0 – D7
Individual LEDs
Eight individual LEDs driven by the FPGA.
U8, U9
Seven-segment LEDs
Two seven-segment LEDs that display numeric
output from the FPGA.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)