Altera Nios Development Board Cyclone II Edition User Manual
Page 30
2–18
Reference Manual
Altera Corporation
Nios Development Board Cyclone II Edition
May 2007
Board Components
G25
14
J11
proto1_io11
G26
15
J11
proto1_io12
H23
16
J11
proto1_io13
H24
17
J11
proto1_io14
J23
18
J11
proto1_io15
J24
21
J11
proto1_io16
H25
23
J11
proto1_io17
H26
25
J11
proto1_io18
K18
27
J11
proto1_io19
K19
28
J11
proto1_io20
K23
29
J11
proto1_io21
K24
31
J11
proto1_io22
J25
32
J11
proto1_io23
J26
33
J11
proto1_io24
M21
35
J11
proto1_io25
T23
36
J11
proto1_io26
R17
37
J11
proto1_io27
K21
38
J11
proto1_cardsel_n
P17
39
J11
proto1_io28
J12
Y22
3
J12
proto1_io40
T18
4
J12
proto1_io29
T17
5
J12
proto1_io30
U26
6
J12
proto1_io31
R19
7
J12
proto1_io32
T19
8
J12
proto1_io33
U20
9
J12
proto1_io34
U21
10
J12
proto1_io35
V26
11
J12
proto1_io36
V25
12
J12
proto1_io37
V24
13
J12
proto1_io38
V23
14
J12
proto1_io39
J13
U2 pin 19
9
J13
proto1_osc
Table 2–11. PROTO1 Pin Table (Continued)
FPGA Pin
PROTO1 Pin
Connector
Board Net Name
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)