Ssram chip (u74), Ssram chip (u74) –6, Table 2–5 – Altera Nios Development Board Cyclone II Edition User Manual
Page 18
2–6
Reference Manual
Altera Corporation
Nios Development Board Cyclone II Edition
May 2007
Board Components
SSRAM Chip
(U74)
U74 is a 32-bit, 2 Mbyte Cypress SSRAM chip. Depending on the board
revision, the part number is CY7C1380C-167AC or CY7C1380D-167AXC.
The chip is rated for synchronous accesses up to 167 MHz. U74 connects
to the FPGA so it can be used by a Nios II embedded processor as general-
purpose memory. The factory-programmed Nios II reference design
identifies the SSRAM devices in its address space as a contiguous 2
Mbyte, 32-bit-wide, zero-wait-state main memory.
Table 2–5. Dual Seven-Segment Display
FPGA Pin
U8 & U9 Pin
Pin Function
Board Net Name
U8
AE13
10
a
hex_0A
AF13
9
b
hex_0B
AD12
8
c
hex_0C
AE12
5
d
hex_0D
AA12
4
e
hex_0E
Y12
2
f
hex_0F
V11
3
g
hex_0G
U12
7
dp
hex_0DP
U9
V14
10
a
hex_1A
V13
9
b
hex_1B
AD11
8
c
hex_1C
AE11
5
d
hex_1D
AE10
4
e
hex_1E
AF10
2
f
hex_1F
AD10
3
g
hex_1G
AC11
7
dp
hex_1DP
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)