Altera SDI Audio IP Cores - Manual (Page 9)

• Specify options for processing the IP core files in other EDA tools.
4. Click Finish or Generate to generate synthesis and other optional files matching your IP variation
specifications. The parameter editor generates the top-level .qip or .qsys IP variation file and HDL files
for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design
for hardware testing.
5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench
System is not available for some IP cores that do not provide a simulation testbench.
6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example.
Generate > HDL Example is not available for some IP cores.
The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in
Project to manually add a
.qip or .qsys file to a project. Make appropriate pin assignments to connect ports.
Simulating Altera IP Cores in other EDA Tools
The Quartus II software supports RTL- and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation
model libraries, and running your simulation.
You can use the functional simulation model and the testbench or example design generated with your IP
core for simulation. The functional simulation model and testbench files are generated in a project
subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list
of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.
NativeLink launches your preferred simulator from within the Quartus II software.
Figure 2-3: Simulation in Quartus II Design Flow
Altera IP supports a variety of simulation models, including simulation-specific IP functional
simulation models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate Note:
models. The models support fast functional simulation of your IP core instance using industry-
standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is
generated, and you can simulate that model. Use the simulation models only for simulation and not
for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.
Related Information
Simulating Altera Designs
SDI Audio IP Getting Started Altera Corporation
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Simulating Altera IP Cores in other EDA Tools 2-4
2014.06.30