Altera SDI Audio IP Cores - Manual (Page 16)

SDI Clocked Audio Output IP Core
The SDI Clocked Audio Output IP core accepts clocked Avalon-ST audio and converts to audio in modified
AES formats.
SDI Audio Clocked Audio Output Parameters
The following table lists the parameters for the SDI Clocked Audio Output IP cores.
Table 3-4: SDI Clocked Audio Output Parameters
Description Value Parameter
Defines the internal FIFO depth.
For example, a value of 3 means 2³ = 8.
3–10 FIFO size
Turn on to include the Avalon-MM control interface.
When you turn on this parameter, the register interface signals appear at
the top level. Otherwise, the direct control interface signals appear at the
top level.
On or
Off Include Avalon-MM
control interface
AES Format
The SDI cores use the AES standard. The Audio Engineering Society (AES), together with the European
Broadcasting Union (EBU), created a digital audio transmission standard known as the AES/EBU standard.
The AES standard is a digital audio standard for transporting digital audio signals serially between devices.
Using the AES format requires the entire 64-bit AES frame to be sent serially. As the AES defines the preambles
as biphase mark codes, which cannot be directly decoded to 4 bits, you must replace the preambles with X
= 0000b, Y = 0001b, and Z = 0010b. This internal AES format serializes the bit-parallel data words by sending
the least significant bits (LSB) first, with the audio sample (up to 24 bits).
This figure shows the timing diagram of the internal AES format.
Figure 3-4: Internal AES Format Timing Diagram
clock
aud_de
aud_ws
aud_data
Channel
Status
Parity
Y Preamble
LSB = 1
Z/X Preamble
1/0
Word n - Left Channel 32 bits
Z/X Preamble
LSB = 0
Altera Corporation SDI Audio IP Functional Description
Send Feedback
3-7 SDI Clocked Audio Output IP Core
UG-SDI-AUD
2014.06.30