Altera SDI Audio IP Cores - Manual (Page 29)

Description Direction Width Signal
Audio word select. Input [0:0]
aes_ws
Audio data input in internal AES format. Input [0:0] aes_data
This table lists the Avalon-ST audio signals when you instantiate the SDI Audio Clocked Input IP core in
Qsys.
Table 4-13: SDI Audio Clocked Input Avalon-ST Audio Signals
Description Direction Width Signal
Clocked audio clock. All the audio input signals are synchronous
to this clock. Input [0:0]
aud_clk
Avalon-ST ready signal. Assert this signal when the device is able
to receive data. Input [0:0] aud_ready
Avalon-ST valid signal. The core asserts this signal when it produces
data. Output [0:0]
aud_valid
Avalon-ST start of packet signal. The core asserts this signal when
it is starting a new frame. Output [0:0]
aud_sop
Avalon-ST end of packet signal. The core asserts this signal when
it is ending a frame. Output [0:0]
aud_eop
Avalon-ST data bus. The core asserts this signal to transfer data. Output [23:0]
aud_data
This table lists the direct control interface signals. The direct control interface is internal to the audio extract
component.
Table 4-14: SDI Audio Clocked Input Direct Control Interface Signals
Description Direction Width Signal
Indicates the channel number of audio channel 1. Input [7:0]
channel0
Indicates the channel number of audio channel 2. Input [7:0]
channel1
Drive bit 7 high to reset the clocked audio input FIFO buffer. Input [7:0]
fifo_status
Assert this signal when the clocked audio input FIFO buffer
overflows. Output [0:0]
fifo_reset
Related Information
SDI Audio IP Register Interface Signals on page 4-10
All SDI Audio IP cores use the same register interface signals.
SDI Audio Clocked Output Signals
The following tables list the signals for the SDI Audio Clocked Output IP cores.
Altera Corporation SDI Audio IP Interface Signals
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4-9 SDI Audio Clocked Output Signals
UG-SDI-AUD
2014.06.30