Altera SDI Audio IP Cores - Manual (Page 36)

Table 5-3: SDI Audio Extract Register Map
Name Bytes Offset
Audio Control Register 00h
Audio Presence Register 01h
Audio Status Register 02h
SD EDP Presence Register 03h
Error Status Register 04h
Reserved 05h
FIFO Status Register 06h
Clock Status Register 07h
Reserved 08h-09h
Channel Status RAM (0×00), (0×01), ... (0×2F) 10h-3Fh
Table 5-4: SDI Audio Extract Registers
Description Access Name Bit
Audio Control Register
Enables the audio extraction component and internal AES
output. RW Enable 0
Defines the audio pair that the component extracts. For
example:
• [000] = Extract the first channel pair of audio signal
• [111] = Extract the eighth channel pair of audio signal
RW Extract pair 3:1
For 3G-SDI Level A standard, this field extends the extract
pair field to allow for future implementations with 32
embedded audio channels.
For 3G-SDI Level B standard, this field selects the active
video half of the 3G multiplex.
RW Extract pair MSB 4
Drive this register high to mute the audio output. RW Mute 5
Reserved for future use. — Unused 7:6
Altera Corporation SDI Audio IP Registers
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5-5 SDI Audio Extract Registers
UG-SDI-AUD
2014.06.30