Sdi audio ip design example, Components of design example, Sdi audio ip design example -1 – Altera SDI Audio IP Cores User Manual
Page 41: Components of design example -1
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SDI Audio IP Design Example
2014.06.30
UG-SDI-AUD
Altera provides a design example with the SDI Audio Embed and Extract IP cores. This design example
includes the SDI Audio IP cores and instances of the SDI IP cores.
This section discusses the requirements and related procedures to demonstrate the SDI Audio example
design with the Stratix IV GX Audio Video Development Kit.
Components of Design Example
This figure shows a high-level block diagram of the design example.
Figure 6-1: High-Level Block Diagram of Stratix IV GX FPGA
Video Pattern
Generator P0
Audio Pattern
Generator
Ancillary Data
Insertion P1
Video Pattern
Generator P1
(internal AES)
(internal AES)
aud_data
aud_ws
aud_de
aud_data
aud_ws
aud_de
AES
Stratix IV GX FPGA
Encrypted IP core
Ancillary Data
Insertion P0
Transceiver Dynamic
Reconfiguration
Control Logic
Waveform
Monitor
(WFM 700)
Audio Embed P0
SDI TX P0
SDI_OUT_2
SDI_OUT_1
AES_IN_1
AES_OUT_1
SDI_IN_1
Audio Extract
Audio Embed P1
AES Output Module
AES Input Module
SDI Duplex
RX
TX P1
The following sections describe the various elements in design example.
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