Altera SDI Audio IP Cores - Manual (Page 20)

5. Click Finish.
6. In the IP Catalog (Tools > IP Catalog), locate and double-click the variant audio_embed_avalon_top.v
file.
The SDI Audio Embed parameter editor appears.
7. In the SDI Audio Embed parameter editor, click Finish to regenerate the variant
audio_embed_avalon_top.v file and produce the simulation model.
8. Repeat steps 6 to 9 for the remaining variant files in the megacore_build directory.
9. In a text editor, open the simulation script, simulation/run.tcl. Edit the script to point to your installation
of the Quartus II software.
For example,
set quartusdir /tools/acds/14.0/157/linux32/quartus/eda/sim_lib/
10. Start the ModelSim simulator.
11. Run run.tcl in the simulation directory. This file compiles the design.
A selection of signals appears on the waveform viewer. The simulation runs automatically, providing a
pass or fail indication upon completion.
Guidelines
When you use the testbench to simulate the IP cores, consider the following guidelines:
• Select the video standard for the video test source through the generic
G_TEST_STD
of the testbench entity.
Set 0, 1, 2 or 3 to select SD-SDI, HD-SDI, 3G-SDI Level A, or 3G-SDI Level B.
• The audio test source uses the 48-kHz clock output from the SDI Audio Embed IP core. The audio test
sample comprises an increasing count which allows the testbench to check the extracted audio at the far
end of the processing chain.
• The SDI Audio Embed IP core accepts these video and audio test sources to create a video stream with
embedded audio. The SDI Audio Extract IP core then receives the resulting stream to recover the embedded
audio. Examine this audio sequence to ensure that the count pattern that was created is preserved.
• The synchronisation requirements of the receive FIFO buffer in the SDI Audio Extract IP core allows
you to repeat the occasional sample from the SDI Audio Extract IP core. Synchronisation may take up
to a field period of typically 16.7 ms to complete.
• Select
G_INCLUDE_AVALON_ST = 1
, if you want to instantiate another SDI Audio Embed IP core with
Avalon-ST interface (with embedded clocked audio output component) and the associated SDI Audio
Extract IP core with Avalon-ST interface (with embedded clocked audio input component) in this
testbench.
Altera Corporation SDI Audio IP Functional Description
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3-11 Guidelines
UG-SDI-AUD
2014.06.30