Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 60)

A–28 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
Figure A–29 shows an example of a clock-pair = CLK11 to CLK6
Figure A–29. Inter-Clock Domain with Two Independent Clocks and Cascaded PLLs on Both Source and
Destination Clocks
Table A–29 shows input of the PLL index for Figure A–29 , with respect to
the source and destination clocks.
PLL5 PLL9
INBUF3
Source
Clock
Source
Register
Destination
Register
CLK10 CLK11
PLL4 PLL3
INBUF4
Destination
Clock
CLK5 CLK6
Table A–29. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
5 9 4 3