Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 47)

Altera Corporation A–15
HardCopy II Clock Uncertainty Calculator User Guide
Figure A–16 shows an example of a clock-pair = CLK6 to CLK7
Figure A–16. Intra-Clock Domain with Cascaded PLLs and 2 PLL Outputs
Table A–16 shows input of the PLL index for Figure A–16 , with respect to
the source and destination clocks.
INBUF
PLL9 PLL11
CLK6
CLK7
Source
Clock
Destination
Clock
Source
Register
Destination
Register
CLK5
Table A–16. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
9 11 9 11