Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 55)

Altera Corporation A–23
HardCopy II Clock Uncertainty Calculator User Guide
Figure A–24 shows an example of a clock-pair = CLK7 to CLK12
Figure A–24. Inter-Clock Domain with Cascaded PLLs and Two PLLs on the Source Clock and Two PLLs on
the Destination Clock
Table A–24 shows input of the PLL index for Figure A–24 , with respect to
the source and destination clocks.
PLL4 PLL3
INBUF
Source
Clock
Source
Register
Destination
Register
CLK6 CLK7
PLL5 PLL8
Destination
Clock
CLK11 CLK12
Table A–24. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
4 3 5 8