Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 48)

A–16 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
Inter-Clock
Domain with
Cascaded PLLs This section provides clock transfer examples for an inter-clock domain
with cascaded PLLs.
Figure A–17 shows an example of a clock-pair = CLK7 to CLK9
Figure A–17. Inter-Clock Domain with Cascaded PLLs on Destination Clock
Table A–17 shows input of the PLL index for Figure A–17 , with respect to
the source and destination clocks.
INBUF
PLL3 PLL5
CLK7
CLK9
Source
Clock
Destination
Clock
Source
Register
Destination
Register
CLK2
Table A–17. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
0 — 3 5