Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 54)

A–22 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
Figure A–23 shows an example of a clock-pair = CLK3 to CLK6
Figure A–23. Inter-Clock Domain with Cascaded PLLs and One Shared and One on Source Clock and One on
Destination Clock
Table A–23 shows input of the PLL index for Figure A–23 , with respect to
the source and destination clocks.
INBUF
PLL12
CLK3
CLK6
Source
Clock
Destination
Clock
Source
Register
Destination
Register
CLK2
CLK5
PLL3
PLL7
Table A–23. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
12 3 12 7