Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 3)

Altera Corporation iii
August 2007
Contents
Chapter 1. About HardCopy II Clock Uncertainty Calculator
Introduction ............................................................................................................................................ 1–1
General Description ............................................................................................................................... 1–2
PLL Extraction .................................................................................................................................. 1–3
Clock Transfer Report ...................................................................................................................... 1–4
Intra-Clock Transfer ................................................................................................................... 1–5
Inter-Clock Transfer .................................................................................................................... 1–5
I/O Transfer ................................................................................................................................. 1–6
Clock Uncertainty Calculator Spreadsheet ................................................................................... 1–6
Instructions .................................................................................................................................. 1–6
Clock Uncertainty Calculator .................................................................................................... 1–7
Advanced Clock Uncertainty Calculator ................................................................................. 1–7
Chapter 2. Launching the HardCopy II Clock Uncertainty Calculator
Release Information ............................................................................................................................... 2–1
Device Family Support ......................................................................................................................... 2–1
System and Software Requirements ................................................................................................... 2–2
Download and Install the HardCopy II Clock Uncertainty Calculator ................................... 2–3
Installation of HardCopy II Clock Uncertainty Calculator ........................................................ 2–3
Running the Clock Uncertainty Calculator Flow .............................................................................. 2–3
PLL Settings Summary Extraction ................................................................................................. 2–3
Syntax ........................................................................................................................................... 2–3
Running get_pll.tcl on the Quartus II Tcl Console ................................................................. 2–4
Running get_pll.tcl on the Command Line or UNIX ............................................................. 2–4
Report Clock Transfers Using the TimeQuest Timing Analyzer .............................................. 2–5
Run HardCopy II Clock Uncertainty Calculator Spreadsheet .................................................. 2–6
Using the Clock Uncertainty Calculator .................................................................................. 2–6
Using the Advanced Clock Uncertainty Calculator .............................................................. 2–8
Create Clock Uncertainty Timing Constraints on a SDC ......................................................... 2–11
Chapter 3. Design Case Exceptions
Multiple Clock Uncertainty on a Single Clock Transfer .................................................................. 3–1
Various Clock Structures ...................................................................................................................... 3–2
Clock Gated in Core ......................................................................................................................... 3–2
Clock Divider .................................................................................................................................... 3–3
Ripple Clock ...................................................................................................................................... 3–3
Multiple Clock Networks ................................................................................................................ 3–4
Multi-Cycle Clock ............................................................................................................................. 3–4