Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 53)

Altera Corporation A–21
HardCopy II Clock Uncertainty Calculator User Guide
Figure A–22 shows an example of a clock-pair = CLK7 to CLK10
Figure A–22. Inter-Clock Domain with Cascaded PLLs on the Source Clock and One PLL on the Destination
Clock
Table A–22 shows input of the PLL index for Figure A–22 , with respect to
the source and destination clocks.
INBUF
Source
Clock
Destination
Clock
Source
Register
Destination
Register
PLL4
PLL11
CLK2 CLK10
CLK5
PLL6
CLK7
Table A–22. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
4 6 11 —