Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 49)

Altera Corporation A–17
HardCopy II Clock Uncertainty Calculator User Guide
Figure A–18 shows an example of a clock-pair = CLK4 to CLK7
Figure A–18. Inter-Clock Domain with Cascaded PLLs on the Source Clock
Table A–18 shows input of the PLL index for Figure A–18 , with respect to
the source and destination clocks.
INBUF
CLK1
CLK7
Source
Clock
Destination
Clock
Source
Register
Destination
Register
PLL9 PLL11
CLK4
Table A–18. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
9 1 0 —