Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 45)

Altera Corporation A–13
HardCopy II Clock Uncertainty Calculator User Guide
Figure A–13 shows an example of a clock-pair = Off-chip to CLK8
Figure A–13. Input Interface without PLL
Table A–13 shows input of the PLL index for Figure A–13 , with respect to
the source and destination clocks.
1 If no PLL exists, enter “ 0” for both the source and destination
clocks.
Figure A–14 shows an example of a clock-pair = CLK12 to Off-chip
Figure A–14. Output Interface without a PLL
INBUF
CLK8
Destination
Register
DATA
Destination
Clock
Table A–13. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
0 — 0 —
INBUF
CLK12
Source
Register
DATA
Source
Clock