ADLINK ReadyBoard 910 - Manual (Page 36)

Chapter 3 Hardware
30 Reference Manual ReadyBoard 910
Note: The shaded table cells denote power or ground.
LVDS Interface
Table 3-9 lists the pin signals for the LVDS header, which provides 42 pins, two rows, odd/even (1,2) pin
sequence with 0.049" (1.25mm) pitch.
21 NC Not Connected
22 NC Not Connected
Table 3-9. LVDS Interface Pin Signals (CN5)
Pin # Signal Description Line Channel
1 +12V +12 volt input
NA NA
2 +VCC (+3.3V/+5V) JP1 determines voltage on pin
3 GND Ground
4 +VCC (+3.3V/+5V) JP1 determines voltage on pin
5 LA_DATA0_P Data Positive Output 0
Channel 1
6 GND Ground
7 LA_DATA0_N Data Negative Output 0
8 LA_DATA1_P Data Positive Output 1
9 GND Ground
10 LA_DATA1_N Data Negative Output 1
11 LA_DATA2_P Data Positive Output 2
12 GND Ground
13 LA_DATA2_N Data Negative Output 2
14 LA_DATA3_P Data Positive Output 3
15 GND Ground
16 LA_DATA3_N Data Negative Output 3
17 LB_CLOCK_P Clock Positive Output Clock
Channel 2 18 GND Ground
19 LB_CLOCK_N Clock Negative Output Clock
20 LA_CLOCK_P Clock Positive Output Clock
Channel 1 21 GND Ground
22 LA_CLOCK_N Clock Negative Output Clock
Table 3-8. DVI Pin Signal Descriptions (CN4) (Continued)