Compaq 21264 - Manual (Page 221)

Alpha 21264/EV67 Hardware Reference Manual Initialization and Configuration 7–13
Initialization Mode Processing
Except for INIT_MODE, all the CSR registers have been described in earlier sections.
When asserted, INIT_MODE has the following behavior:
• Cache block updates to the Dcache set the block to the Clean state.
• Updates to the Bcache use the BC_WRT_STS[3:0] bits.
• WrVictimBlk command generation to the system interface are squashed.
Using the INVAL_TO_DIRTY_ENABLE and INIT_MODE registers, initialization
code loaded from the SROM can generate and delete blocks inside the 21264/EV67
without system interaction. This behavior is very useful for initialization and startup
processing, when the system interfaces are not fully functional. Figure 7–4 shows a
code example for initializing Bcache.
Figure 7–4 Example for Initializing Bcache
Reset chip and load Icache with this code
set init_mode ;now all WrVictims are ignored
;bc_enable_a 1
;zeroblk_enable_a 1
;set_dirty_enable_a 0
;init_mode_a 1
;enable_evict_a 0
;bc_wrt_sts_a 0
;bc_bank_enable_a 0
;bc_size_a 15
;now all writes to Bcache actually invalidate
;the Bcache. (if space was needed for scratch
;pad, the status bits could just as
;well be Valid)
for 2 X bc_size ;This loop generates legal ECC data, and
{ WH64 address } ;invalidate tags which are written to the
;Bcache for all but the final 64KB of address.
turn_off_bcache: ;bc_enable_a 0
;init_mode_a 0
;bc_size_a 0
;zeroblk_enable_a 1
;enable_evict_a 0
;set_dirty_enable_a 0
;bc_bank_enable_a 0
;bc_wrt_sts_a 0
EVICT_ENABLE 0
BC_WRT_STS[3:0] 0
BC_BANK_ENABLE 0
Table 7–9 WRITE_MANY Chain CSR Values for Bcache Initialization
WRITE_MANY Chain CSRs Required Value at Initialization Mode