Compaq 21264 User Manual
Page 300
D–2
PALcode Restrictions and Guidelines
Alpha 21264/EV67 Hardware Reference Manual
Restriction 1 : Reset Sequence Required by Retire Logic and Mapper
addt f31,f31,f2
/* initialize F.P. Reg. 2*/
mult f31,f31,f3
/* initialize F.P. Reg. 3*/
addq r31,r31,r4
/* initialize Int. Reg. 4*/
addq r31,r31,r5
/* initialize Int. Reg. 5*/
addt f31,f31,f4
/* initialize F.P. Reg. 4*/
mult f31,f31,f5
/* initialize F.P. Reg. 5*/
addq r31,r31,r6
/* initialize Int. Reg. 6*/
addq f31,r31,r7
/* initialize Int. Reg. 7*/
addt f31,f31,f6
/* initialize F.P. Reg. 6*/
mult f31,f31,f7
/* initialize F.P. Reg. 7*/
addq r31,r31,r8
/* initialize Int. Reg. 8*/
addq r31,r31,r9
/* initialize Int. Reg. 9*/
addt f31,f31,f8
/* initialize F.P. Reg. 8*/
mult f31,f31,f9
/* initialize F.P. Reg. 9*/
addq r31,r31,r10
/* initialize Int. Reg. 10*/
addq r31,r31,r11
/* initialize Int. Reg. 11*/
addt f31,f31,f10
/* initialize F.P. Reg. 10*/
mult f31,f31,f11
/* initialize F.P. Reg. 11*/
addq r31,r31,r12
/* initialize Int. Reg. 12*/
addq r31,r31,r13
/* initialize Int. Reg. 13*/
addt f31,f31,f12
/* initialize F.P. Reg. 12*/
mult f31,f31,f13
/* initialize F.P. Reg. 13*/
addq r31,r31,r14
/* initialize Int. Reg. 14*/
addq r31,r31,r15
/* initialize Int. Reg. 15*/
addt f31,f31,f14
/* initialize F.P. Reg. 14*/
mult f31,f31,f15
/* initialize F.P. Reg. 15*/
addq r31,r31,r16
/* initialize Int. Reg. 16*/
addq r31,r31,r17
/* initialize Int. Reg. 17*/
addt f31,f31,f16
/* initialize F.P. Reg. 16*/
mult f31,f31,f17
/* initialize F.P. Reg. 17*/
addq r31,r31,r18
/* initialize Int. Reg. 18*/
addq r31,r31,r19
/* initialize Int. Reg. 19*/
addt f31,f31,f18
/* initialize F.P. Reg. 18*/
mult f31,f31,f19
/* initialize F.P. Reg. 19*/
addq r31,r31,r20
/* initialize Int. Reg. 20*/
addq r31,r31,r21
/* initialize Int. Reg. 21*/
addt f31,f31,f20
/* initialize F.P. Reg. 20*/
mult f31,f31,f21
/* initialize F.P. Reg. 21*/
addq r31,r31,r22
/* initialize Int. Reg. 22*/
addq r31,r31,r23
/* initialize Int. Reg. 23*/
addt f31,f31,f22
/* initialize F.P. Reg. 22*/
mult f31,f31,f23
/* initialize F.P. Reg. 23*/
addq r31,r31,r24
/* initialize Int. Reg. 24*/
addq r31,r31,r25
/* initialize Int. Reg. 25*/
addt f31,f31,f24
/* initialize F.P. Reg. 24*/
mult f31,f31,f25
/* initialize F.P. Reg. 25*/
addq r31,r31,r26
/* initialize Int. Reg. 26*/