Achronix Speedster22i HD1000 Development Kit User Guide - Manual (Page 67)

UG034, July 1, 2014 67
Switch
Function
Connection
No Position Through Pin Signal
SW14 1 Clock select input 31 E_SEL1_2
2 Clock select input 30 E_SEL0_2
SW5 1 Clock select input U19 31 E_SEL1_3
2 Clock select input 30 E_SEL0_3
SW2 1 PLL/Bypass mode 40 E_VCCO_SEL_3
2 Output divider value 11 E_NA2_3
3 Output divider value 10 E_NA1_3
4 Output divider value 9 E_NA0_3
5 Output divider value 4 E_NB2_3
6 Output divider value 3 E_NB1_3
7 Output divider value 2 E_NB0_3
8 Clock divider input 1 E_M8_3
SW1 1 Clock divider input 48 E_M7_3
2 Clock divider input 47 E_M6_3
3 Clock divider input 46 E_M5_3
4 Clock divider input 45 E_M4_3
5 Clock divider input 44 E_M3_3
6 Clock divider input 43 E_M2_3
7 Clock divider input 42 E_M1_3
8 Clock divider input 41 E_M0_3
SW6 1 J14 30 PRG_CNTL1
2 31 PRG_CNTL2
3 32 PRG_CNTL3
4 46 PRTADR0
5 45 PRTADR1
6 44 PRTADR2
7 43 PRTADR3
8 42 PRTADR4
SW10 1 U33 AJ49 BYTEIO8_DQ2_P
2 AF48 BYTEIO8_DQ3_N
3 AE48 BYTEIO8_DQ4_P
4 AE49 BYTEIO8_DQ5_N
5 AC48 BYTEIO8_DQ6_P
6 AF49 BYTEIO8_DQ7_N
7 AD49 BYTEIO8_DQ8_P
8 AC49 BYTEIO8_DQ9_N
SW8 1 J18 HDR_BYPASS_CLR_MEM
2 K19 HDR_CFG_SCR_ENABLE
3 K14 HDR_CFG_STARTUP
SW9 1 U101 25 PCIE_CLK_FSEL0
2 24 PCIE_CLK_FSEL1
3 6 PCIE_CLK_FSEL2
4 U7 27 CLK_SEL_FMC
SW11 1 U72 27 CLK_SEL_INTLKN
2 U57 16 CLK_SEL
3 U5 6 SMP_CLK_SEL
* For all DIP switches except for DIP switch 11, “on” = 0.