Achronix Speedster22i HD1000 Development Kit User Guide User Manual
Page 53
UG034, July 1, 2014
53
Table 20: Sample DIP Switch Settings to Generate Desired Synthesizer Output Clocks
M Counter (SW12)
N Counter (SW13)
M/N
Output
Freq (MHz)
M5 M4 M3 M2 M1 M0 M Value Nx2 Nx1 Nx0
N Value
0
1
0
1
0
0
20
1
1
0
8
2.5
62.5
0
1
0
1
0
1
21
1
1
0
8
2.625
65.625
0
1
0
1
1
0
22
1
1
0
8
2.75
68.75
0
1
0
1
1
1
23
1
1
0
8
2.875
71.875
0
1
1
0
0
0
24
1
1
0
8
3
75
0
1
1
0
0
1
25
1
1
0
8
3.125
78.125
0
1
0
1
0
0
20
1
0
1
6
3.33
83.33
0
1
0
1
0
1
21
1
0
1
6
3.50
87.50
0
1
0
1
1
0
22
1
0
1
6
3.67
91.67
0
1
0
1
1
1
23
1
0
1
6
3.83
95.83
0
1
1
0
0
0
24
1
0
1
6
4
100
0
1
0
1
0
1
21
1
0
0
5
4.2
105
0
1
0
1
1
0
22
1
0
0
5
4.4
110
0
1
0
1
1
1
23
1
0
0
5
4.6
115
0
1
1
0
0
0
24
1
0
0
5
4.8
120
0
1
1
0
0
1
25
1
0
0
5
5
125
0
1
0
1
0
1
21
0
1
1
4
5.25
131.25
0
1
0
1
1
0
22
0
1
1
4
5.5
137.5
0
1
0
1
1
1
23
0
1
1
4
5.75
143.75
0
1
1
0
0
0
24
0
1
1
4
6
150
0
1
1
0
0
1
25
0
1
1
4
6.25
156.25
0
1
0
1
0
0
20
0
1
0
3
6.67
166.67
0
1
0
1
0
1
21
0
1
0
3
7
175
0
1
0
1
1
0
22
0
1
0
3
7.33
183.33
0
1
0
1
1
1
23
0
1
0
3
7.67
191.67
0
1
1
0
0
0
24
0
1
0
3
8
200
Default FPGA GPIO Clk for Banks NW & SW
* For this DIP switche that controls the clock synthesizer settings, “on” = 0.
U19 provides 30 – 350 MHz LVPECL outputs that are used by the Interlaken SerDes North on
the HD1000. These outputs (SYN_IK1_CLK_P, SYN_IK1_CLK_N) are one of two pairs
presented to the input pins of the IDT ICS853310 device (U72). The second differential input
pair is (INTERLAKEN1_RX_CLK_N, INTERLAKEN1_RX_CLK_P). You can use the
CLK_SEL_INTLKN (SW11) signal to choose the clock source for the Interlaken SerDes on the
HD1000. Table 21 shows the connections from the IDT ICS853310 device (U72) to the
HD1000.
Table 21: Interlaken SerDes Clocks and their Connections
Signal Name
Pin on HD1000 (U33)
Pin on ICS853310 (U72)
INTERLAKEN1_CLK1_P
BC32
23
INTERLAKEN1_CLK1_N
BB32
21