Achronix Speedster22i HD1000 Development Kit User Guide - Manual (Page 11)

UG034, July 1, 2014 11
ACX-BRD-HD1000-100G Development Board Features
FPGA

Achronix 22-nm, AC22IHD1000-F53C3
Functional blocks

1 million equivalent LUTs (700k programmable LUTs + hardened IP)

86 Mbit on-chip memory (82 Mb BRAM, 4 Mb LRAM)

756 28x28 multiply/accumulate blocks

960 programmable user IOs
Networking and Communications

Hardened Ethernet MACs: 100GE, 40GE, 10GE

64 SerDes lanes (1 to 12.75 Gb/s)

Hardened Interlaken ports, each running up to 11.3Gbps
System

Hardened PCI Express Gen1/2/3 x1, x4, x8

Hardened DDR3 controllers: six x72 at 2.133 Gb/s
Board

PCI Express pluggable form factor

Six SMAs (Tx, Rx, Clk) for single lane SerDes access

DDR3 SO-DIMM socket

One DDR3 device

Power supply modules

Power on reset circuitry

Oscillators/ crystals/ clock modules & synthesizers

Power and temperature measurement sensors

SPI header for FLASH access

FLASH for device configuration

LEDs, switches, headers
Interfaces
Networking and Communications

CFP cage for 100GE line interface

Adaptable to 2x40GE or 10x10GE

Interlaken interface (AirMax connector pair)

135Gb/s to companion board/system

FMC expansion port (HPC)

Ten SerDes lane at 10 Gb/s

Up to 160 signals (or 80 diff) at 1.6 Gb/s