Achronix Speedster22i HD1000 Development Kit User Guide - Manual (Page 30)

30 UG034, July 1, 2014
Signal Name SerDes No Pin on HD1000 (U33)
CFP1_RX_N9 F28
CFP1_TX_P9 A28
CFP1_TX_N9 B28
SERDES_CFP1_CLK1_P M31
SERDES_CFP1_CLK1_N N31
Interlaken Interface (AirMax Connector Pair)
The Interlaken interface provides a secondary high-speed datapath. You can use this to
enable interoperation with other packet-processing devices such as ASICs and/or Network
Processors. In such operation, you can implement certain decision making functions on the
the HD1000 prior to presenting the Ethernet packet to the Network Processing Unit (NPU).
The board uses dual AirMax connectors (one for Tx, the second for Rx). The interface
supports 12 x 11.3 Gb/s bandwidth.
Figure 11 shows the Interlaken Interface, and Table 5 and Table 6, the associated pins. These
are designated SerDes Top 20 – 31 in Figure 9 for the HD1000.
Table 5: ACX-BRD-HD1000-100G Interlaken Transmitter Interface Pins
Signal Name SerDes No
Pin on HD1000
(U33)
Pin on Header
(J1)
INTERLAKEN_TX_P0
20 – 21
BJ31 A7
INTERLAKEN_TX_N0 BK31 B7
INTERLAKEN_TX_P1 BK32 D6
INTERLAKEN_TX_N1 BL32 E6
INTERLAKEN1_CLK6_P BC28 NA
INTERLAKEN1_CLK6_N BB28 NA
INTERLAKEN_TX_P2
22 – 23
BK33 D8
INTERLAKEN_TX_N2 BJ33 E8
INTERLAKEN_TX_P3 BL34 A9
INTERLAKEN_TX_N3 BK34 B9
INTERLAKEN1_CLK5_P BC29 NA
INTERLAKEN1_CLK5_N BB29 NA
INTERLAKEN_TX_P4
24 – 25
BK35 A3
INTERLAKEN_TX_N4 BJ35 B3
INTERLAKEN_TX_P5 BK36 D2
INTERLAKEN_TX_N5 BL36 E2
INTERLAKEN1_CLK4_P AY31 NA
INTERLAKEN1_CLK4_N AW31 NA
INTERLAKEN_TX_P6
26 – 27
BK37 D4
INTERLAKEN_TX_N6 BJ37 E4
INTERLAKEN_TX_P7 BK38 A5
INTERLAKEN_TX_N7 BL38 B5
INTERLAKEN1_CLK2_P AY32 NA
INTERLAKEN1_CLK2_N AW32 NA
INTERLAKEN_TX_P8
28 – 29
BK39 G5
INTERLAKEN_TX_N8 BJ39 H5
INTERLAKEN_TX_P9 BK40 G3
INTERLAKEN_TX_N9 BL40 H3
INTERLAKEN1_CLK3_P BC31 NA