Achronix Speedster22i HD1000 Development Kit User Guide - Manual (Page 24)

24 UG034, July 1, 2014
Pin Name on HD
1000 (U33)
x1 Boot from Flash
(Serial Mode) - EFC
CPU Mode
CPU_CLK CPU CLOCK --
CONFIG_RSTN Active-low configuration reset
CONFIG_DONE Open-drain configuration done output
CONFIG_STATUS Open-drain SRAM initialization complete output
CONFIG_MODESEL
[2:0]
Must be : ‘100’ Must be : ‘010’
CONFIG_SYSCLK_
BYPASS
Bypass configuration sys
clock : Don’t Care
Bypass configuration sys clock : Set to ‘0’
CONFIG_CLKSEL Select Configuration Clock : Set to ‘0’
JTAG
The development PC provides the bitstream source to configure the HD1000. You download
this to the board using the JTAG connection, the Bitporter pod and either the ACE
environment or a command line interface.
Serial
In this mode, the FPGA is configured from the Serial Flash (U78).
CPU
In this mode, the FPGA is configured from the MicroSD card.
FLASH Programming
You can program the Flash using the JTAG interface with the jumper (J31) position at 1&2.
Once you program the FPGA and see the CONFIG_DONE LED light green, this means that
the configuration has successfully completed and that the part has transitioned to user mode.
At this point, you can run your application as desired.