Achronix Speedster22i HD1000 Development Kit User Guide - Manual (Page 42)

42 UG034, July 1, 2014
Signal Name Pin on HD1000 (U33) Pin on MT41J128M16JT (U21)
DDR3_BA1 AD1 N8
DDR3_BA2 AN2 M3
DDR3_CK AF10 J7
DDR3_CK_N AF9 K7
DDR3_CKE AN4 K9
DDR3_CS_N AT4 L2
DDR3_WE_N AF1 L3
DDR3_RAS_N AE2 J3
DDR3_CAS_N AJ2 K3
DDR3_RST_N AP4 T2
DDR3_ODT AM3 K1
DDR3_LDQS0 AY2 F3
DDR3_LDQS0_N AY1 G3
DDR3_UDQS0 AF13 C7
DDR3_UDQS0_N AF14 B7
DDR3_LDM0 AU2 E7
DDR3_UDM0 AC14 D3
RLDRAM3 Devices (U31, U36)
You can use the two 16 Mbx36 RLDRAM3 memory devices (Micron MT44K32M18RB-093)
soldered on the board. The HD1000 drives the memory signals using dedicated GPIOs.
Although you may repurpose these IO pins, Bank West-South (Byte 0 – 12), on your designs,
you must maintain the allocation shown in Table 14 to use the devices provided on the
board.
Note: Do not reallocate these Ios on the ACX-BRD-HD1000-100G development board. This could
lead to unexpected behavior.
Note: Table 14 shows only the logical connection for application development. Relevant voltage levels
are driven on the board by additional circuitry.
Table 14: ACX-BRD-HD1000-100G Memory Interfaces – RLDRAM3
Signal Name Pin on HD1000 (U33)
Pin on MT44K32M18RB
(U31) (U36)
RLD_DQ0 U11 D11
RLD_DQ1 V11 E10
RLD_DQ2 AA11 C8
RLD_DQ3 T11 C10
RLD_DQ4 T12 C12
RLD_DQ5 AB11 B9
RLD_DQ6 Y12 B11
RLD_DQ7 AB12 A8
RLD_DQ8 AA12 A10
RLD_DQ9 T4 J10
RLD_DQ10 U3 K11
RLD_DQ11 T3 K13
RLD_DQ12 AB4 L8
RLD_DQ13 W4 L10
RLD_DQ14 V3 L12