Qdr2+ device (72 mb) – Achronix Speedster22i HD1000 Development Kit User Guide User Manual
Page 45
UG034, July 1, 2014
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Signal Name
Pin on HD1000 (U33)
Pin on MT44K32M18RB
(U31)
(U36)
RLD_QK1
AA3
K9
RLD_QK1_N
AA4
J8
RLD_QK2
V9
D5
RLD_QK2_N
V10
E6
RLD_QK3
P3
K5
RLD_QK3_N
P4
J6
RLD_DK0
P11
D7
RLD_DK0_N
P12
C7
RLD_DK1
G3
K7
RLD_DK1_N
G4
L7
RLD_DM2
J1
B7
RLD_DM3
R6
M7
RLD_QK4
M1
D9
RLD_QK4_N
M2
E8
RLD_QK5
L5
K9
RLD_QK5_N
L6
J8
RLD_QK6
M7
D5
RLD_QK6_N
M8
E6
RLD_QK7
P9
K5
RLD_QK7_N
P10
J6
RLD_DK2
D1
D7
RLD_DK2_N
D2
C7
RLD_DK3
D5
K7
RLD_DK3_N
D6
L7
Note: TDI, TDO, TMS and TCK (pins N10, N4, N12, and N2) are jumpered using J517 and J516 to
the device (U31) pins and J544 and J545 to the device (U36) pins.
QDR2+ Device (72 Mb)
You can use the Cypress Semiconductor CY7C2565XV18, 72 Mb QDR2+ memory device
soldered on the board. The HD1000 drives the memory signals using dedicated GPIOs.
Although you may repurpose these IO pins, Bank East-North (Byte 0 – 12), on your designs,
you must maintain the allocation shown in Table 15 to use the device provided on the board.
Note: Do not reallocate these Ios on the ACX-BRD-HD1000-100G development board. This could
lead to unexpected behavior.
Note: Table 15 shows only the logical connection for application development. Relevant voltage levels
are driven on the board by additional circuitry.
Table 15: ACX-BRD-HD1000-100G Memory Interfaces
– CY7C2565XV18
Signal Name
Pin on HD1000 (U33)
Pin on CY7C2565XV18 (U22)
QDR2_Q0
AW42
P11
QDR2_Q1
AY43
M10
QDR2_Q2
BA42
L11
QDR2_Q3
BB43
K11
QDR2_Q4
BC42
J10
QDR2_Q5
BB41
F11
QDR2_Q6
AW40
E11