Rockwell Automation 1785-Vx0B, D17856.5.9 PLC-5 VME VMEbus Programmable Controllers User Manual - Manual (Page 173)

Sample API Modules
Appendix B
B-15
/*****************************************************************************
*
* PURPOSE: This function will enable the 64K of shared RAM that is
* present on the PLC-5/40V.
*
* INPUT: ULONG baseAddress contains the base address of the PLC-5/40V.
*
* ULONG vmeSharedRAMAddr contains the VME address of the
* shared ram on the PLC-5/40V that is
* specified in the baseAddress field.
*
* OUTPUT: PLC540V_STATUS_TYPE *status will contain the final status
* of requesting this function. This status could be and EPC
* or PLC-5/40V value.
*
* RETURNS: Nothing.
*
* EXAMPLE:
* ULONG baseAddress = 0xFC00;
* ULONG vmeSharedRAMAddr = 0x60000;
* PLC540V_STATUS_TYPE *status;
* plc540v_enable_shared_memory(baseAddress,
* vmeSharedRAMAddr,
* &status);
*
* Copyright Allen-Bradley Company, Inc. 1993
*
****************************************************************************/
void plc540v_enable_shared_memory(ULONG baseAddress,
ULONG vmeSharedRAMAddr,
PLC540V_STATUS_TYPE *status)
{
UWORD offsetReg = 0;
UWORD statCtrlReg = 0;
/* Convert the VME shared RAM address to the OFFSET register format. */
offsetReg = MK_OFFSET(vmeSharedRAMAddr);
/* Write this value into the PLC-5/40V’s OFFSET register. */
write_plc540v_register(baseAddress,
kPLC540V_OF_REG,
offsetReg,
status);
if (status->plc540vStatus == kPLC540V_SUCCESS)
{
/* Now we must enable the PLC-5/40V’s shared memory. This is done
by setting the SLAVE ENABLE bit in the PLC-5/40V’s
STATUS/CONTROL register.
*/
read_plc540v_register(baseAddress, kPLC540V_SC_REG,
&statCtrlReg, status);
if (status->plc540vStatus == kPLC540V_SUCCESS)
{
statCtrlReg |= kPLC540V_ENABLE_STATCTRL_SLE;
write_plc540v_register(baseAddress,
kPLC540V_SC_REG,
statCtrlReg,
status);
}
}
}