IEI Integration NANO-HM650 - Manual (Page 35)

NANO-HM650 EP IC S BC
P a g e 20
Figure 3-6: DDR3 SO-DIMM Socket Location
3.2.6 De b u g P o rt Co n n e c to r
CN La b e l: DEBUGCN1
CN Typ e : 9-pin wafer
CN Lo c a tio n : See Figure 3-7
CN P in o u ts : See Table 3-7
The debug port connector is for system debug.
Figure 3-7: Debug Port Connector Location
Pin Description
1 PLT_RST#
2 LPC_DEBUG_CLK
3 GND