IEI Integration NANO-9452 v1.00 - Manual (Page 170)

NANO-9452 EPIC Motherboard
Page 152
Use the Configure DRAM Timing by SPD option to determine if the system uses the
SPD (Serial Presence Detect) EEPROM to configure the DRAM timing. The SPD
EEPROM contains all necessary DIMM specifications including the speed of the individual
components such as CAS and bank cycle time as well as valid settings for the module and
the manufacturer's code. The SPD enables the BIOS to read the spec sheet of the DIMMs
on boot-up and then adjust the memory timing parameters accordingly.
Disabled DRAM timing parameters are manually set using the
DRAM sub-items
Enabled D EFAULT DRAM timing parameter are set according to the
DRAM Serial Presence Detect (SPD)
If the Configure DRAM Timing by SPD option is disabled, the following configuration
options appear.
DRAM CAS# Latency [3]
DRAM RAS# to CAS# Delay [5 DRAM Clocks]
DRAM RAS# Precharge [5 DRAM Clocks]
DRAM RAS# Activate to Precha [15 DRAM Clocks]
DRAM CAS# Latency [3]
Use the CAS Latency Time configuration option to set the Column Address Strobe (CAS)
delay time. (To be able to change this configuration option the DRAM Latency Timing
configuration option must be set to “Manual”) The following configuration options are
available
5 nanoseconds
4 nanoseconds
3 nanoseconds D EFAULT
DRAM RAS# to CAS# Delay [5 DRAM Clocks]
Use the DRAM RAS# to CAS# Delay option to specify the number of clock cycles must
elapse between sending a RAS (row address strobe) signal and the CAS (column address