Rainbow Electronics AT76C551 - Manual (Page 48)

48
AT76C551
1612D–08/01
• Bit 3 – DIR: Audio Clock Direction
1= Digital interface is slave
0= Digital interface is master
• Bit 2 – BDIV: Divides Audio Clock
Divides Audio Clock (depending on mode[4] bit) in order to drive the bit clock.
{mode[2], mode[4]} = 00, abclk = aclk/32
{mode[2], mode[4]} = 01, abclk = aclk/16
{mode[2], mode[4]} = 10, abclk = aclk/24
{mode[2], mode[4]} = 11, abclk = aclk/12
• Bits 1..0 – M_CDC[1:0]: Master Audio Clock Divider Control
00 = aclk is driven by mclock
01 = aclk = mclock/2
10 = aclk = mclock/4
11 = aclk = mclock/8
Note: Default Value: 0000 hex
The digital interface is able to operate either as a master or a slave. When operating as a mas-
ter, a 6.144 MHz clock is used, while in slave mode, the clock available at the ABCLK_IN pin is
used to drive the digital interface.
VC_INT_CTRL_STATUS: Voice CODEC Interrupt Control Status
addr: 500008 hex R/W 16 bits
• Bits 15..4 – Reserved
• Bit 3 – EN_RC_I:Enable Voice CODEC Transmit FIFO Interrupt
• Bit 2 – EN_TR_I: Enable Voice CODEC Receive FIFO Interrupt
• Bit 1 – VCRC_S: Transmit FIFO Interrupt Status
• Bit 0 – VCTR_S: Receive FIFO Interrupt Status
Note: Default Value: 0000 hex
VC_RxFifoCtrl: Voice CODEC Receive FIFO Control Status Register ()
addr: 50000C hex R/W 16 bits
• Bit 15 – EMPTY
• Bit 14 – ALEMPTY
1 byte left to be transmitted.
• Bit 13 – FULL
• Bit 12 – RESFF: Reset Receive FIFO
• Bits 11..10 – Reserved
• Bits 8..5 – RCFTR[4:0]: Receive FIFO Threshold
• Bits 1..0 – LEVEL[4:0]: Receive FIFO Level
Note: Default Value: 0000 hex