Rainbow Electronics AT76C551 - Manual (Page 20)

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AT76C551
1612D–08/01
Voice CODEC The voice CODEC module supports both CVSD (Continuous Variable Slope Delta) coding and
log PCM coding (A-law and U-law). The coded voice data from both coding algorithms will be
transferred with a constant bit rate of 64 kbits/sec.
The voice CODEC hardware consists of the following modules: A digital-to-analog converter
(D/AC) for converting linear PCM data to the analog domain, an analog-to-digital converter
(ADC), a digital interface for connection of external integrated voice codecs, a codec submod-
ule, which implements the CVSD and log PCM alogrithms and two 32-byte FIFOs which are
capable of holding 4 ms of coded voice data in each direction. Interrupts are generated when
a programmable level of data in the FIFOs has been reached. Two externally connected low-
pass filters are required to use a microphone and earphones.
Coded voice data from the Bluetooth interface can be transferred to an external voice codec
through a digital interface. This interface can be configured as either a master or a slave. The
interface accepts two possible clock formats: Short Frame Sync and Long Frame Sync.
USB Function
Interface The USB functionality is executed by an USB hardware block and firmware running on the
ARM controller. This configuration allows acceleration of the intensive function processing
while allowing flexibility in the implementation of higher level protocols over USB.
The USB hardware block consists of a Serial Interface Engine (SIE), a Serial Bus Controller
(SBC) and a System Interface. The SIE performs the clock/data separation, NRZI encoding
and decoding, bit insertion and deletion, CRC generation and checking, and the serial-parallel
data conversion. The SBC consists of a protocol engine and a USB device with 6 endpoints,
each with dedicated double buffered FIFOs. One endpoint has an 8-byte FIFO, two endpoints
have 16-byte FIFOs, two have 32-byte FIFOs and two have 128-byte FIFOs. The SBC man-
ages the device address, monitors the status of the transactions, manages the FIFOs and
communicates to the processor through a set of status and control registers. The System
Interface connects the Serial Bus Controller to the processor.
16550 Compatible
UART The UART hardware module is a universal asynchronous receiver and transmitter with 16-
byte Transmit and Receive FIFO. A programmable baud rate generator is provided to select,
transmit and receive clock rates from 1200 bps to 921 Kbps.
The input clock to the baud rate generator is generated from a 96 MHz clock (derived from the
internal clock generator). The required division ratios and the relative error are shown in Table
1 for a 96 MHz clock.