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Mac interface registers – Rainbow Electronics AT76C551 User Manual

Page 29

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29

AT76C551

1612D–08/01

MAC Interface
Registers

MAC Interface Registers (MIR) lie in the PCMCIA interface unit. They are mapped into AMBA
memory space, i.e. they are directly accessible by the ARM core but they are not directly
accessible by the host. MIRs allow AT76C551 firmware to communicate with the host and to
generate interrupts to the host processor.

MIR0 – PIR1: Processor Interface Register 1

addr: 800000 hex

R/W

16 bits

• Bits 15..4 – PIR1[15:4]

General purpose I/O

Bits 15..8 are reflected to bits 7..0 of MR2 so that the host can read them.

Bits 7..0 are reflected to bits 7..0 of MR1 so that the host can read them.

• Bit 3 – HIA: Host Interrupt to ARM

This bit is set if an interrupt to the ARM core has been generated by the host (see bit HIA of
SIR0) and is still pending. To acknowledge the interrupt and clear this bit, AT76C551 firmware
must write 1 on this bit.

• Bit 2 – AIH: ARM Interrupt to Host

When this bit is set by the ARM core, an interrupt to the host is generated (see bit AIH of
SIR0). This bit is automatically cleared when the host acknowledges the interrupt.

• Bit 1 – HIAEN: Host to ARM Interrupt Enable

Logic 0: Interrupts from the host to ARM core disabled

Logic 1: Interrupts from the host to ARM core enabled

• Bit 0 – Reserved

Note:

Default Value: 0000 hex

MIR1 – PIR2: Processor Interface Register 2

addr: 800004 hex

R/W

16 bits

• Bits 15..8 – PIR2[15:8]

General purpose I/O

MIR1 bits 15..8 are reflected to bits 7..0 of MR4 so that the host can read them.

• Bits 7..0 – PIR2[7:0] General purpose I/O

MIR1 bits 7..0 are reflected to bits 7..0 of MR3 so that the host can read them.

Note:

Default Value: 0000 hex

Table MIR2 – PIR3: Processor Interface Register 3

addr: 800008 hex

R/W

16 bits

• Bits 15..8 – PIR3[15:8]

General purpose I/O

MIR2 bits 15..8 are reflected to bits 7..0 of MR6

so that the host can read them.

• Bits 7..0 – PIR3[7:0]

General purpose I/O

MIR2 bits 7..0 are reflected to bits 7..0 of MR5 so that the host can read them.

Note:

Default Value: 0000 hex