Rainbow Electronics AT76C551 - Manual (Page 24)

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AT76C551
1612D–08/01
PCMCIA
Configuration
Registers The PCMCIA configuration registers are required by the PCMCIA standard. These registers
are mapped into PCMCIA attribute memory space to allow the host to configure basic param-
eters of the PCMCIA device. They are accessible by the host but they are not accessible by
ARM core.
COR: Configuration Option Register
PCMCIA addr: 0800 hex R/W 8 bits
• Bit 7 – SRES: System Reset
By setting this bit, the device is reset in a way equivalent to PCMCIA hardware reset signal
activation.
Note: Tthis bit is not automatically cleared after set.
• Bit 6 – IEVREQ
Logic 1: Level mode interrupt.
Logic 0: Pulse mode interrupt
• Bits 5..0 – CFX[5:0]: Configuration Index
This field is written with the index number of the entry in the card’s configuration table which
the host selects. When all the field bits are zero, the device is in memory only mode.
Note: Default Value: 00 hex
CSR: Configuration and Status Register
PCMCIA addr: 0802 hex R/W 8 bits
• Bits 7..6 – Reserved
• Bit 5 – IOIS8
Logic 1: The host is only capable of 8-bit I/O accesses.
Logic 0: The host is capable of 8-bit and 16-bit I/O accesses.
• Bits 4..0 – Reserved
Note: Default Value: 00 hex
System Interface
Registers The System Interface Registers (SIR) lie in the PCMCIA interface unit. They are mapped into
PCMCIA I/O space, i.e. they are directly accessible by the host but they are not directly acces-
sible by the ARM core. They allow the host to configure and communicate with AT76C551
through host I/O space.
Note: All AMBA memory space (16M bytes address space) can be accessed by the host through the
PCMCIA interface unit, via SIR1 - SIR5.
SIR0 – GCR: General Configuration Register
PCMCIA addr: 0000 hex R/W 8 bits
Bit 7 – SWRES: Software Reset
By setting this bit, all SIR registers are reset. However, AT76C551 units on the AMBA bus
(ARM core, PAI, etc.) are not be reset by SWRES bit activation. This bit is automatically
cleared after set.