Intel 460GX User Manual
Page 45
Intel® 460GX Chipset Software Developer’s Manual
2-25
Register Descriptions
Default Value:
00h
Attribute:
Read/Write Clear
Sticky:
Yes
Locked:
No
These registers record and latch the first error detected in the AGP interface.
Bits
Description
7:6
reserved (0)
5
Lo-priority Read Data Que Parity Error
This is data returned to the graphics card out of the Low-priority buffer.
4
Hi-priority Read Data Que Parity Error
This is data returned to the graphics card out of the Hi-priority buffer.
3
Use of Pipe with Sideband Enabled
2
AGP address from graphics card [63:40] not equal to 0
1
AGP Request Queue Overflow
The GXB supports 16 outstanding requests. This bit is set if a new request is sent by the
AGP card when the GXB already has 16 requests.
0
Illegal AGP Command
2.4.5.4
FERR_GART: First Error Status Register for GART
Function Number:
BFN+1
Address Offset:
86h
Size:
8 bits
Default Value:
00h
Attribute:
Read/Write Clear
Sticky:
Yes
Locked:
No
These registers record and latch the first error detected in the AGP interface.
Bits
Description
7:4
reserved (0)
3
GART Parity Error.
2
GART Entry Invalid
1
Illegal Address (after GART translation) in range between GAPBAS and GAPTOP, or
in VGA range and VGAGE is asserted, or directed by MARG to PCI instead of memory,
or above TOM.
0
reserved (0)
2.4.5.5
NERR_AGP: Next Errors Status Register for AGP
Function Number:
BFN+1
Address Offset:
8Dh
Size:
8 bits
Default Value:
00h
Attribute:
Read/Write Clear
Sticky:
Yes
Locked:
No
This register records all error conditions detected in the AGP interface after the first error. Errors
recorded in FERR_AGP are not recorded here.
Bits
Description
7:0
See FERR_AGP for definition of these bits.