Intel 460GX User Manual
Page 30
Register Descriptions
2-10
Intel® 460GX Chipset Software Developer’s Manual
2.4.1.8
BIUDATA: BIU Data Register
Bus CBN, Device Number: 00h
Function:
1
Address Offset:
90h
Size:
128 bits
Default Value:
undefined
Attribute:
Read Only
Sticky:
No
Locked:
No
This is the contents of the CAM concatenated with the contents of the RAM associated with the
ITID in BIUITID.
Bits
Description
127:116
reserved(0)
115:82
Address bits [35:2].
This is the contents of the CAM with address bits [5:2] from the RAM (bit 2 is only of
interest if the transaction came from an Expander bus).
81:76
reserved(0)
75:71
Reqa. Request phase a[4:0].
70:63
DID. The DID for the transaction.
62:55
BE. The byte enables for the transaction.
54
reserved (0)
53
OWN. OWN# active.
52
DPS. DPS# active.
51:49
Reqb. Request phase b bits [4:2].
48
Lock. The transaction.had LOCK# asserted.
47
LockLoad. The transaction is the first occurrence of an OB lock sequence.
46:43
Dst. The destination of the transaction.
42
ORetry. A retry due to HITO.
41:36
CMD. The command for the transaction.
35
P2P. Set for peer-to-peer transactions.
34
FEorR. The end-of-request bit from the Expander port.
33:30
FRoute. The Expander bus route.
29:22
FLEN. The length on the Expander bus.
21:12
FTID. The Expander id.
11:9
Len. The length of the transaction.
8
System Bus Retry. The transaction was retried on the bus.
7
Dfr. The transaction is deferred.
6
MEM. The target for the transaction if memory.
5
System Bus. The target for the transaction is the system bus.
4
CLINE. The transaction is for a full line.
3
Zero. If set then this is a 0-length transaction.
2:0
RS. The Response generated for the transaction by the BIU. This may not match the
system bus response sent, since the BIU’s response may be changed by the MIU. This
may be for a HITM# or other reasons.
Note:
Note: if the P2P bit is not set, then bits [34:12] and [76] are not defined, since the transaction
originated on the system bus and not the Expander bus.