Intel 460GX - Manual (Page 193)

Intel® 460GX Chipset Software Developer’s Manual 11-3
LPC/FWH Interface Configuration
11.1.5 RID–Revision Identification Register (Function 0)
Address Offset: 08h
Default Value: Stepping Dependent
Attribute: Read Only
This 8 bit register contains device stepping information. Writes to this register have no effect.
11.1.6 CLASSC–Class Code Register (Function 0)
Address Offset: 09h-0Bh
Default Value: 060100h
Attribute: Read Only
This register identifies the Base Class Code, Sub-class Code, and Device Programming interface
for the IFB PCI Function 0.
11.1.7 HEDT–Header Type Register (Function 0)
Address Offset: 0Eh
Default Value: 80h
Attribute: Read Only
The HEDT Register identifies the IFB as a multi-Function device.
8 PERR# Response (Not Implemented). Read as 0.
7 Fast Back to Back–RO. This bit indicates to the PCI Master that IFB as a target is capable of
accepting fast back-to-back transactions. This bit is hardwired to 1.
6:0 Reserved.
Bit Description
Bit Description
7:0 Revision ID Byte.
Bit Description
23:16 Base Class Code (BASEC). 06h=Bridge device.
15:8 Sub-Class Code (SCC). 01h=PCI-to-ISA Bridge. ISA is not supported, IFB forwards cycles to
the LPC interface.
7:0 Programming Interface (PI). 00h=No register level programming interface defined.
Bit Description
7:0 Device Type (DEVICET). 80h=multi-Function device.