Intel 460GX - Manual (Page 161)

Intel® 460GX Chipset Software Developer’s Manual 8-15
WXB Hot-Plug
into this register. Writing a logic 1 will clear the pending interrupt. If there are no other pending
interrupts on the bit, the bit will clear. This register takes on a value based on the monitored status
of the slots and therefore has no particular default value.
Bits Description
31:30 reserved (0)
29 Slot F PRSNT(0)#, PCI Present Signal 1
28 Slot E PRSNT(0)#, PCI Present Signal 1
27 Slot D PRSNT(0)#, PCI Present Signal 1
26 Slot C PRSNT(0)#, PCI Present Signal 1
25 Slot B PRSNT(0)#, PCI Present Signal 1
24 Slot A PRSNT(0)#, PCI Present Signal 1
23:22 reserved (0)
21 Slot F PRSNT(1)#, PCI Present Signal 2
20 Slot E PRSNT(1)#, PCI Present Signal 2
19 Slot D PRSNT(1)#, PCI Present Signal 2
18 Slot C PRSNT(1)#, PCI Present Signal 2
17 Slot B PRSNT(1)#, PCI Present Signal 2
16 Slot A PRSNT(1)#, PCI Present Signal 2
15:14 reserved (0)
13 Slot F FAULT#, PCI Power Fault Signal
12 Slot E FAULT#, PCI Power Fault Signal
11 Slot D FAULT#, PCI Power Fault Signal
10 Slot C FAULT#, PCI Power Fault Signal
9 Slot B FAULT#, PCI Power Fault Signal
8 Slot A FAULT#, PCI Power Fault Signal
7:6 reserved(0)
5 Slot F Hot-Plug Switch, 0 = lever closed (board installed)
4 Slot E Hot-Plug Switch, 0 = lever closed (board installed)
3 Slot D Hot-Plug Switch, 0 = lever closed (board installed)
2 Slot C Hot-Plug Switch, 0 = lever closed (board installed)
1 Slot B Hot-Plug Switch, 0 = lever closed (board installed)
0 Slot A Hot-Plug Switch, 0 = lever closed (board installed)
8.2.6 Hot-Plug Interrupt Mask
Address Offset: 0Ch Size: 32 bits
Default Value: FFFFFFFFh Attribute: Read/Write
This read/write mask register is used to indicate which inputs should generate interrupts and which
should not. The mask bits in this register map one-for-one with the HIICR (Interrupt Input and
Clear Register) bits. If a state change occurs on an input while the mask bit for that input is set to
one, then no interrupt will be generated for that state change. If the mask bit is cleared, then an
interrupt will be generated on the next state change.