Intel 460GX - Manual (Page 41)

Intel® 460GX Chipset Software Developer’s Manual 2-21
Register Descriptions
This register records and latches the data corresponding to the first DED detected by system bus
interface in the SDC.
Bits Description
63:0 DE - System Data of Error.
2.4.2.30 DEDF_ECC_FERR: ECC on First System Bus DED
Bus CBN, Device Number: 04h
Address Offset: F8h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first DED detected by
system bus interface in the SDC.
Bits Description
7:0 ECC - ECC of Error.
2.4.2.31 DEDF_TXINFO_FERR: TXINFO on First System Bus DED
Bus CBN, Device Number: 04h
Address Offset: F9-FAh Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first DED detected by system
bus interface in the SDC.
Bits Description
15:9 reserved(0)
8:6 DC - Data Chunk of ITID.
5:0 ITID - ITID of error.
2.4.3 MAC
2.4.3.1 FERR_MAC: First Error Status Register
Bus CBN, Device Number: 05h,06h Function Number: 00h,01h
Address Offset: 98h Size: 8 bits
Default Value: 00h Attribute: Read
This register records the first error condition detected in the MAC.
Bits Description
7:2 reserved(0)
1 Que-Overflow Error
Signals that the MAC received too many commands from the SAC.