Intel 460GX - Manual (Page 40)

Register Descriptions
2-20 Intel® 460GX Chipset Software Developer’s Manual
2.4.2.26 SECF_D_FERR: Data on First System Bus SEC
Bus CBN, Device Number: 04h
Address Offset: E0-E7h Size: 64 bits
Default Value: 0 Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the data corresponding to the first SEC detected by system bus
interface in the SDC.
Bits Description
63:0 DE - System Data of Error.
2.4.2.27 SECF_ECC_FERR: ECC on First System Bus SEC
Bus CBN, Device Number: 04h
Address Offset: E8h Size: 8 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records and latches the ECC checkbits corresponding to the first SEC detected by
system bus interface in the SDC.
Bits Description
7:0 ECC - ECC of Error.
2.4.2.28 SECF_TXINFO_FERR: TXINFO on First System Bus SEC
Bus CBN, Device Number: 04h
Address Offset: E9-EAh Size: 16 bits
Default Value: 00h Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
This register records the ITID and failing chunk corresponding to the first SEC detected by system
bus interface in the SDC.
Bits Description
15:9 reserved(0)
8:6 DC - Data Chunk of error.
5:0 ITID - ITID of error.
2.4.2.29 DEDF_D_FERR: Data on First System Bus DED
Bus CBN, Device Number: 04h
Address Offset: F0-F7h Size: 64 bits
Default Value: 0 Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set