BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 84)

IP Core Signals
III-72 Slave Controller – IP Core for Xilinx FPGAs
8.6.4.1 8 Bit µController Interface
Table 30 lists the signals used with an 8 Bit µC PDI.
Table 30: 8 Bit µC PDI
Condition Name Direction Description
Tristate drivers inside
core (µController
configuration)
PDI_uC_DATA[7:0] BIDIR µC data bus
External tristate drivers
PDI_uC_DATA_IN[7:0] INPUT
µC data bus:
µC  IP Core
PDI_uC_DATA_OUT[7:0] OUTPUT
µC data bus :
IP Core  µC
8.6.4.2 16 Bit µController Interface
Table 31 lists the signals used with a 16 Bit µC PDI.
Table 31: 16 Bit µC PDI
Condition Name Direction Description
Tristate drivers inside
core (µController
configuration)
PDI_uC_DATA[15:0] BIDIR µC data bus
External tristate drivers
PDI_uC_DATA_IN[15:0] INPUT
µC data bus:
µC  IP Core
PDI_uC_DATA_OUT[15:0] OUTPUT
µC data bus:
IP Core  µC