BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual
Page 143

Synthesis Constraints
Slave Controller
– IP Core for Xilinx FPGAs
III-131
##################
### MII Port 2 ###
##################
### Receive clock period 40 ns/25 MHz ###
TIMESPEC TS_RX_CLK2 = PERIOD TM_RX_CLK2 40000 ps;
Net MII_RX_CLK2 TNM_NET = TM_RX_CLK2;
### RX_DV/RX_DATA setup 10 ns, hold 10 ns ###
OFFSET = IN 10 ns VALID 20 ns BEFORE MII_RX_CLK2;
### TX_ENA/TX_DATA maximum clock-to-pad 10 ns ###
### (manually check minimum clock-to-pad = 0 ns) ###
### TX_CLK from PHY to REF_CLK phase shift has to be ###
### determined and compensated using TX-Shift or registers ###
TIMEGRP TM_TX2 OFFSET = OUT 10 ns AFTER REF_CLK;
Net MII_TX_ENA2 TNM_NET=TM_TX2;
Net MII_TX_DATA2<0> TNM_NET=TM_TX2;
Net MII_TX_DATA2<1> TNM_NET=TM_TX2;
Net MII_TX_DATA2<2> TNM_NET=TM_TX2;
Net MII_TX_DATA2<3> TNM_NET=TM_TX2;
- Bus Terminal System (19 pages)
- EP-xxxx-xxxx (19 pages)
- BK2000 (30 pages)
- LC3100 (67 pages)
- BK4000 (28 pages)
- BK3xx0 (95 pages)
- BK5000 (12 pages)
- LC5200 (32 pages)
- BK7000 (29 pages)
- BK7500 (32 pages)
- BK7300 (40 pages)
- BK8100 (26 pages)
- BC2000 (28 pages)
- BC3100 (51 pages)
- BC7300 (48 pages)
- BC8100 (36 pages)
- BC3150 (112 pages)
- KL1012 (2 pages)
- KL1114 (2 pages)
- KL1164 (1 page)
- KL1232-xxxx (4 pages)
- KL1501 (19 pages)
- KL1512 (15 pages)
- KL2521-0024 (18 pages)
- KL2512 (21 pages)
- KL2612 (4 pages)
- KL2622 (9 pages)
- KL3062 (24 pages)
- KL3064 (20 pages)
- KL4132 (19 pages)
- KL4034 (25 pages)
- KL3302 (23 pages)
- KL3351 (18 pages)
- KS3681 (43 pages)
- KL4112 (18 pages)
- KL5001 (16 pages)
- KL5051 (17 pages)
- KL5101-0012 (21 pages)
- KS5111-0000 (21 pages)
- KL5121 (19 pages)
- KL6021 (20 pages)
- KL6051 (17 pages)
- Z1000 (2 pages)
- KL6071 (12 pages)
- Z1003 (2 pages)