BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 39)

IP Core Installation
Slave Controller – IP Core for Xilinx FPGAs III-27
3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow
3.8.1 Software Templates for example designs with Microblaze/ARM processor (EDK)
Software example templates are available for EDK example designs with Microblaze/ARM processor.
The templates have to be copied to your EDK installation folder.
Copy everything inside the templates folder
\example_designs\SDK_application_templates
to your EDK installation folder
\ISE_DS\EDK\sw\lib\sw_apps\
On Windows, the IP Core installation tries to identify EDK installations and integrates the templates
automatically.
For stand-alone SDK installations, copy the templates to your SDK installation folder:
\sw\lib\sw_apps
3.8.2 Software Templates for example designs with ARM processor (Vivado)
Software example templates are available for Vivado example designs with ARM processor. The
templates have to be copied to your Vivado SDK installation folder.
Copy everything inside the templates folder
\example_designs\Vivado_SDK_application_templates
to your Vivado SDK installation folder
\SDK\\data\embeddedsw\lib\sw_apps\
3.9 EtherCAT Slave Information (ESI) / XML device description for example designs
If you want to use the example designs, add the ESI to your EtherCAT master/EtherCAT configuration
tool/network configurator.
The ESI is located at
\example_designs\EtherCAT_Device_Description\BECKHOFF ET1815.xml
If you are using TwinCAT, add the ESI to the appropriate folder of your TwinCAT installation before
the System Manager is started:

TwinCAT 2: \Io\EtherCAT

TwinCAT 3: \\Config\Io\EtherCAT