BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 111)

PDI Description
Slave Controller – IP Core for Xilinx FPGAs III-99
10.2.3 SPI access
Each SPI access is separated into an address phase and a data phase. In the address phase, the SPI
master transmits the first address to be accessed and the command. In the data phase, read data is
presented by the SPI slave (read command) or write data is transmitted by the master (write
command). The address phase consists of 2 or 3 bytes depending on the address mode. The number
of data bytes for each access may range from 0 to N bytes. The slave internally increments the
address for the following bytes after reading or writing the start address. The bits of both
address/command and data are transmitted in byte groups.
The master starts an SPI access by asserting SPI_SEL and terminates it by taking back SPI_SEL
(polarity determined by configuration). While SPI_SEL is asserted, the master has to cycle SPI_CLK
eight times for each byte transfer. In each clock cycle, both master and slave transmit one bit to the
other side (full duplex). The relevant edges of SPI_CLK for master and slave can be configured by
selecting SPI mode and Data Out sample mode.
The most significant bit of a byte is transmitted first, the least significant bit last, the byte order is low
byte first. EtherCAT devices use Little Endian byte ordering.
10.2.4 Address modes
The SPI slave interface supports two address modes, 2 byte addressing and 3 byte addressing. With
two byte addressing, the lower 13 address bits A[12:0] are selected by the SPI master, while the upper
3 bits A[15:13] are assumed to be 000
b
inside the SPI slave, thus only the first 8 Kbyte in the
EtherCAT slave address space can be accessed. Three byte addressing is used for accessing the
whole 64 Kbyte address space of an EtherCAT slave.
For SPI masters which do only support consecutive transfers of more than one byte, additional
Address Extension commands can be inserted.
Table 48: Address modes
Byte 2 Byte address mode 3 Byte address mode
0 A[12:5] address bits [12:5] A[12:5] address bits [12:5]
1 A[4:0] address bits [4:0]
CMD0[2:0] read/write command
A[4:0] address bits [4:0]
CMD0[2:0] 3 byte addressing: 110b
2 D0[7:0] data byte 0 A[15:13] address bits [15:13]
CMD1[2:0] read/write command
res[1:0]
two reserved bits, set to 00b
3 D1[7:0] data byte 1 D0[7:0] data byte 0
4 ff. D2[7:0] data byte 2 D1[7:0] data byte 1