BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 67)

Example Designs
Slave Controller – IP Core for Xilinx FPGAs III-55
6.3.3 Implementation
1. Open Xilinx Vivado
2. Open project:
\example_designs\ZC702_AXI_VIVADO\ZC702_AXI_VIOVADO.xpr
3. Generate Bitstream
4. Select menu File
– Export – Export hardware, and export the hardware description
5. Launch Vivado SDK
6. In SDK, select menu File
– New – Application Project
7. Create a First Stage Boot Loader (FSBL) project for the Zynq
8. In SDK, select menu File
– New – Application Project
9. Enter a project name, and select project template “BECKHOFF EtherCAT ZC702 AXI”
10. Select Next, then Finish.
11. Select menu Project
– Build All
12. Select Xilinx Tools – Create Zynq Boot Image
13. Add First Stage Boot Loader ELF, FPGA bitstream, and Demo application ELF files
14. Place resulting .bin file in the root folder of the SD card, rename the file to BOOT.bin and configure
the ZC702 to boot from SD card.
6.3.4 SII EEPROM
Use this ESI for the SII EEPROM:
Beckhoff Automation GmbH (Evaluation)/
IP Core example designs ET1815 (Xilinx)/
ET1815 IP Core Xilinx ZC702