BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 4)

CONTENTS
III-IV Slave Controller – IP Core for Xilinx FPGAs
CONTENTS
1 Overview 1
1.1 Frame processing order 2
1.2 Scope of this document 3
1.3 Scope of Delivery 3
1.4 Target FPGAs 4
1.5 Designflow requirements 4
1.6 Tested FPGA/Designflow combinations 5
1.7 Release Notes 6
1.7.1 Major differences between V2.04x and V3.00x 9
1.7.2 Reading IP Core version from device 9
1.8 Design flow 10
1.9 IP Core Evaluation 11
1.10 Simulation 12
2 Features and Registers 13
2.1 Features 13
2.2 Registers 16
2.3 Extended ESC Features in User RAM 19
3 IP Core Installation 23
3.1 Installation on Windows PCs 23
3.1.1 System Requirements 23
3.1.2 Installation 23
3.2 Installation on Linux PCs 24
3.2.1 System Requirements 24
3.2.2 Installation 24
3.3 Files located in the lib folder 24
3.4 License File 25
3.5 IP Core Vendor ID Package 25
3.6 RSA Decryption Keys 26
3.7 Environment Variable 26
3.8 Integrating the EtherCAT IP Core into the Xilinx Designflow 27
3.8.1 Software Templates for example designs with Microblaze/ARM processor
(EDK) 27
3.8.2 Software Templates for example designs with ARM processor (Vivado) 27
3.9 EtherCAT Slave Information (ESI) / XML device description for example designs 27
4 IP Core Usage 28
4.1 IPCore_Config Tool 28
4.2 EDK designs with EtherCAT IP Core 29
4.3 Vivado designs with EtherCAT IP Core 33
5 IP Core Configuration 34
5.1.1 Product ID tab 35